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SP7652
Wide Input Voltage Range 6A, 600kHz, Buck Regulator
FEATURES
* * * * * * * * * * * * * * * * 2.5V to 28V Dual Input Stepdown Output Voltage down to 0.8V 6A Output Capability Built-in Low RDSON Power FETs (15m typ.) Highly Integrated Design, Minimal Components 600kHz Fixed-frequency Operation UVLO Detects Both Vcc and Vin Over Temperature Protection Short Circuit Protection with Auto-Restart Wide Bandwith Amp Allows Type II or III Compensation Programmable Soft Start Fast Transient Response High Efficiency: Greater than 92% Possible Asynchronous Start-Up into a Pre-Charged Output Small 7mm x 4mm DFN Package U.S. Patent #6,922,041
DFN PACKAGE 7mm x 4m m PGND 1 PGND 2 PGND 3 GND 4 VFB 5 COMP 6 UVIN 7 GND 8 SS 9 VIN 10 VIN 11 VIN 12 VIN 13 Heatsink Pad 3 Connect toVIN Heatsink Pad 2 Connect to GND TOP VIEW Heatsink Pad 1 Connect to Lx 26 LX 25 LX 24 LX 23 LX 2 2 VCC 21 GND 20 GND 19 GND 18 BST 17 NC 16 LX 15 LX 14 LX
SP7652
The SP7652 is a synchronous step-down switching regulator optimized for high efficiency. The part is designed to be especially attractive for dual supply, 2V step down with 5V used to power the controller. This lower Vcc voltage minimizes power dissipation in the part. The SP7652 is designed to provide a fully integrated buck regulator solution using a fixed 600kHz frequency, PWM voltage mode architecture. Protection features inc lude UVLO, thermal shutdown and output short circuit protection. The SP7652 is available in the space saving DFN package.
DESCRIPTION
TYPICAL APPLICATION CIRCUIT
00pF 5.K 2.5k ,1% RSET (note 2) nF 2K
2 3 PGND PGND PGND GND VFB COMP UVIN GND SS VIN VIN VIN VIN
U SP7652
LX LX LX LX VCC GND GND GND BST NC LX LX LX 26 25 24 23 22 2 20 19 8 7 6 5 4
68.k ,1%
VOUT 3.3V 0-6A
47uF Ceramic X5R 6.3V
.5uH, Irate=8A
22pF
4 5 6 7
5V VCC CVCC uF
CF 00pF
8 9 0
ENABLE VIN 5V - 20V
C 22uF
CSS 22nF
2 3
5.
SD0AWS
uF
Notes: Notes: .. U bottom-side layout should have U Bottom-Side Layout should have three contacts isolated from one three contacts isolated from one another: Vin,another: VIN, SWNODE, and GND SWnODE, and GND 2.2. RSET = 54.48 / (Vout - 0.8V) (kOhm) RSEt= 54.48 (VOut- 0.8V)(kOhmss)
GND
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SP7652 Wide Input Voltage Range 6A, 600kHz, Buck Regulator
(c) Copyright 2006 Sipex Corporation
These are stress ratings only and functional operation of the device at these ratings or any other above those indicated in the operation sections of the specifications below is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. Storage Temperature ................................................... -65C to 150C Vcc................................................................................................... 7V Power Dissipation ..................................................... Internally Limited Vin .................................................................................................. 30V ESD Rating ........................................................................... 2kV HBM Ilx .................................................................................................. 0A Thermal Resistance Ojc ........................................................... 5C/W BST................................................................................................ 35V LX-BST ...............................................................................-0.3V to 7V LX ........................................................................................-V to 30V All other pins ............................................................-0.3V to Vcc+0.3V
ABSOLUTE MAXIMUM RATINGS
Unless otherwise specified: -40C < Tamb < 85C, -40CELECTRICAL SPECIFICATIONS
PARAMETER QUIESCENT CURRENT Vcc Supply Current (No switching) Vcc Supply Current (switching) BST Supply Current (No switching) BST Supply Current (switching) PROTECTION: UVLO Vcc UVLO Start Threshold Vcc UVLO Hysteresis UVIN Start Threshold UVIN Hysteresis UVIN Input Current ERROR AMPLIFIER REFERENCE Error Amplifier Reference Error Amplifier Reference Over Line and Temperature Error Amplifier Transconductance Error Amplifier Gain COMP Sink Current COMP Source Current Vfb Input Bias Current Internal Pole COMP Clamp COMP Clamp Temp. Coefficient
MIN.
TYP. .5 0.2 8
MAX. 3 5 0.4 2 4.5 300 2.65 400
UNITS mA mA mA mA V mV V mV A * * *
CONDITIONS Vfb =0.9V Vfb =0.9V
4.00 00 2.3 200
4.25 200 2.5 300
UVIN= 3.0V 2X Gain Config., Measure Vfb; Vcc =5V, T=25C *
0.792 0.788
0.800 0.808 0.800 0.82 6 60 50 50 50 4 2.5 -2 200
V V mA/V dB A A nA MHz V mV/C
No Load Vfb =0.9V, COMP= 0.9V Vfb =0.7V, COMP= 2.2V Vfb = 0.8V Vfb =0.7V, TA=25C
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SP7652 Wide Input Voltage Range 6A, 600kHz, Buck Regulator
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Unless otherwise specified: -40C < Tamb < 85C, -40CELECTRICAL SPECIFICATIONS
PARAMETER Ramp Amplitude RAMP Offset until GH starts Switching RAMP Offset Temp. Coefficient GH Minimum Pulsewidth Maximum Controllable Duty Ratio
MIN. 0.92
TYP. . .
MAX. .28
UNITS V V
CONDITIONS
CONTROL LOOP: PWM COMPARATOR, RAMP & LOOP DELAY PATH Ta = 25C, RAMP COMP
-2 90 92 97 80
mV/C ns %
*
Maximum Duty Ratio Measured just before pulsing begins Valid for 20 cycles
*
Maximum Duty Ratio Internal Oscillator Ratio TIMERS: SOFT START SS Charge Current: SS Discharge Current:
00 420 600 0 720
% kHz A mA
*
Fault Present, SS = 0.2V Measured VREf (0.8V) -- Vfb Vfb = 0.5V
PROTECTION: Short Circuit & Thermal Short Circuit Threshold Voltage Hiccup Timeout Number of Allowable Clock Cycles at 100% Duty Cycle Minimum GL Pulse After 20 Cycles Thermal Shutdown Temperature Thermal Recovery Temperature Thermal Hysteresis OUTPUT: POWER STAGE High Side RDSOn Synchronous FET RDSOn Maximum Output Current 6 5 5 m m A Vcc = 5V ; IOut= 6A Tamb = 25C Vcc = 5V ; IOut= 6A Tamb = 25C 0.2 0.25 200 20 0.5 45 35 0 0.3 V ms Cycles Cycles C C C Vfb = 0.7V Vfb = 0.7V
*
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PIN DESCRIPTION
Pin # -3 4,8,19-21 Pin Name PgnD GND Description Ground connection for the synchronous rectifier. Ground Pin. The control circuitry of the IC and lower power driver are referenced to this pin. Return separately from other ground traces to the (-) terminal of COut. Feedback Voltage and Short Circuit Detection pin. The inverting input of the Error Amplifier and serves as the output voltage feedback point for the Buck Converter. The output voltage is sensed and can be adjusted through an external resistor divider. Whenever VFB drops 0.25V below the positive reference, a short circuit fault is detected and the IC enters hiccup mode. Output of the Error Amplifier. Internally connected to the inverting input of the PWM comparator. An optimal filter combination is chosen and connected to this pin and either ground or VFB to stabilize the voltage mode loop. UVLO input for Vin voltage. Connect a resistor divider between Vin and UVin to set minimum operating voltage. Soft Start. Connect an external capacitor between SS and GND to set the soft start rate based on the 0A source current. The SS pin is held low via a mA (min.) current during all fault conditions. Input connection to the high-side N-channel MOSFET. Place a decoupling capacitor between this pin and PGND. Connect an inductor between this pin and VOut. No Connect. High-side driver supply pin. Connect BST to the external boost diode and capacitor as shown in the Typical Application Circuit on page one. High-side driver is connected between BST and SWN pin. Input for external 5V bias supply.
5
Vfb
6 7 9 0-3 4-6,2326 7 8 22
COMP UVIN SS Vin LX NC BST Vcc
General Overview The SP7652 is a fixed frequency, voltage mode, synchronous PWM regulator optimized for high efficiency. The part has been designed to be especially attractive for split plane applications utilizing 5V to power the controller and 3V to 20V for step down conversion. The heart of the SP7652 is a wide bandwidth transconductance amplifier designed to accommodate Type II and Type III compensation schemes. A precision 0.8V reference, present on the positive terminal of the error amplifier, permits the programming of the output voltage down to 0.8V via the Vfb pin. The output of the error amplifier, COMP, which is compared to a .V peak-to-peak ramp, is responsible for trailing edge PWM control. This voltage ramp and PWM control logic are governed by the internal oscillator that accurately sets the PWM frequency to 600kHz.
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THEORY OF OPERATION The SP7652 contains two unique control features that are very powerful in distributed applications. First, asynchronous driver control is enabled during start up, to prohibit the low side NFET from pulling down the output until the high side NFET has attempted to turn on. Second, a 100% duty cycle timeout ensures that the low side NFET is periodically enhanced during extended periods at 100% duty cycle. This guarantees the synchronized refreshing of the BST capacitor during very large duty cycle ratios. The SP7652 also contains a number of valuable protection features. Programmable UVLO allows the user to set the exact Vin value at which the conversion voltage can safely begin down conversion, and an internal Vcc UVLO ensures that the controller itself has enough voltage to operate properly. Other protection features include thermal shutdown and short-circuit detection. In the event that either a thermal, short-circuit, or
(c) Copyright 2006 Sipex Corporation
SP7652 Wide Input Voltage Range 6A, 600kHz, Buck Regulator
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UVLO fault is detected, the SP7652 is forced into an idle state where the output drivers are held off for a finite period before a re-start is attempted. Soft Start Soft start is achieved when a power converter ramps up the output voltage while controlling the magnitude of the input supply source current. In a modern step down converter, ramping up the positive terminal of the error amplifier controls soft start. As a result, excess source current can be defined as the current required to charge the output capacitor. IVin = COut * (VOut / TSOft-StaRt) The SP7652 provides the user with the option to program the soft start rate by tying a capacitor from the SS pin to GND. The selection of this capacitor is based on the 0uA pull up current present at the SS pin and the 0.8V reference voltage. Therefore, the excess source can be redefined as: IVin = COut * (VOut *0A / (CSS * 0.8V) Under Voltage Lock Out (UVLO) The SP7652 contains two separate UVLO comparators to monitor the internal bias (Vcc) and conversion (Vin) voltages independently. The Vcc UVLO threshold is internally set to 4.25V, whereas the Vin UVLO threshold is programmable through the UVIN pin. When the UVIN pin is greater than 2.5V, the SP7652 is permitted to start up pending the removal of all other faults. Both the Vcc and Vin UVLO comparators have been designed with hysteresis to prevent noise from resetting a fault. Thermal and Short-Circuit Protection Because the SP7652 is designed to drive large output current, there is a chance that the power converter will become too hot. Therefore, an internal thermal shutdown (145C) has been included to prevent the IC from malfunctioning at extreme temperatures.
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THEORY OF OPERATION A short-circuit detection comparator has also been included in the SP7652 to protect against an accidental short at the output of the power converter. This comparator constantly monitors the positive and negative terminals of the error amplifier, and if the Vfb pin falls more than 250mV (typical) below the positive reference, a short-circuit fault is set. Because the SS pin overrides the internal 0.8V reference during soft start, the SP7652 is capable of detecting short-circuit faults throughout the duration of soft start as well as in regular operation. Handling of Faults Upon the detection of power (UVLO), thermal, or short-circuit faults, the SP7652 is forced into an idle state where the SS and COMP pins are pulled low and the NFETS are held off. In the event of UVLO fault, the SP7652 remains in this idle state until the UVLO fault is removed. Upon the detection of a thermal or short-circuit fault, an internal 200ms timer is activated. In the event of a short-circuit fault, a re-start is attempted immediately after the 200ms timeout expires. Whereas, when a thermal fault is detected, the 200ms delay continuously recycles and a re-start cannot be attempted until the thermal fault is removed and the timer expires. Error Amplifier and Voltage Loop Since the heart of the SP7652 voltage error loop is a high performance, wide bandwidth transconductance amplifier, great care should be taken to select the optimal compensation network. Because of the amplifier's current limited (150A) transconductance, there are many ways to compensate the voltage loop or to control the COMP pin externally. If a simple, single-pole, single-zero response is desired, then compensation can be as simple as an RC circuit to Ground. If a more complex compensation is required, then the amplifier has enough bandwidth (45C at 4 MHz) and enough gain (60dB) to run Type III compensation schemes with adequate gain and phase margins at cross(c) Copyright 2006 Sipex Corporation
SP7652 Wide Input Voltage Range 6A, 600kHz, Buck Regulator
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THEORY OF OPERATION over frequencies greater than 50kHz. The common mode output of the error amplifier is 0.9V to 2.2V. Therefore, the PWM voltage ramp has been set between .V and 2.2V to ensure proper 0% to 100% duty cycle capability. The voltage loop also includes two other very important features. One is an asynchronous startup mode. Basically, the synchronous rectifier cannot turn on unless the high-side NFET has attempted to turn on or the SS pin has exceeded .7V. This feature prevents the controller from "dragging down" the output voltage during startup or in fault modes. The second feature is a 100% duty cycle timeout that ensures synchronized refreshing of the BST capacitor at very high duty ratios. In the event that the high-side NFET is on for 20 continuous clock cycles, a reset is given to the PWM flip-flop half way through the 2st cycle. This forces GL to rise for the cycle, in turn refreshing the BST capacitor. Power MOSFETs The SP7652 contains a pair of integrated low resistance N-MOSFETs designed to drive up to 6A of output current. Maximum output current could be limited by thermal limitations of a particular application. The SP7652 incorporates a built-in over-temperature protection to prevent internal overheating.
v BsT GH v oltage v sWn v(v CC) GL v oltage 0v sWn v oltage v(v in )
-0v -v(Diode) v v(v in )+v(v CC ) BsT v oltage v(v CC )
TiMe
Setting Output Voltages The SP7652 can be set to different output voltages. The relationship in the following formula is based on a voltage divider from the output to the feedback pin VFB, which is set to an internal reference voltage of 0.80V. Standard 1% metal film resistors of surface mount size 0603 are recommended. VOut = 0.80V (R1/R2+1) => R2= R {(VOut / 0.8V) -1}
Where R1 = 68.1k and for VOut = 0.80V setting, simply remove R2 from the board. Furthermore, one could select the value of the R and R2 combination to meet the exact output voltage setting by restricting R1 resistance range such that 50k < R1 < 100k for overall system loop stability.
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SP7652 Wide Input Voltage Range 6A, 600kHz, Buck Regulator
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Inductor Selection There are many factors to consider in selecting the inductor including core material, inductance vs. frequency, current handling capability, efficiency, size and EMI. In a typical SP7652 circuit, the inductor is chosen primarily by operating frequency, saturation current and DC resistance. Increasing the inductor value will decrease output voltage ripple, but degrade transient response. Low inductor values provide the smallest size, but cause large ripple currents, poor efficiency and require more output capacitance to smooth out the larger ripple current. The inductor must be able to handle the peak current at the switching frequency without saturating, and the copper resistance in the winding should be kept as low as possible to minimize resistive power loss. A good compromise between size, loss and cost is to set the inductor ripple current to be within 20% to 40% of the maximum output current. The switching frequency and the inductor operating point determine the inductor value as follows: L= where: VOut(Vin(max) - VOut) Vin(max)FS*KR*iOut(max)
APPLICATIONS INFORMATION IpEak = iOut(max) + Ipp 2
and provide low core loss at the high switching frequency. Low cost powdered-iron cores are inappropriate for 900kHz operation. Gapped ferrite inductors are widely available for consideration. Select devices that have operating data shown up to MHz. Ferrite materials, on the other hand, are more expensive and have an abrupt saturation characteristic with the inductance dropping sharply when the peak design current is exceeded. Nevertheless, they are preferred at high switching frequencies because they present very low core loss and the design only needs to prevent saturation. In general, ferrite or molypermalloy materials are better choice for all but the most cost sensitive applications. Optimizing Efficiency The power dissipated in the inductor is equal to the sum of the core and copper losses. To minimize copper losses, the winding resistance needs to be minimized, but this usually comes at the expense of a larger inductor. Core losses have a more significant contribution at low output current where the copper losses are at a minimum, and can typically be neglected at higher output currents where the copper losses dominate. Core loss information is usually available from the magnetics vendor. Proper inductor selection can affect the resulting power supply efficiency by more than 15-20%! The copper loss in the inductor can be calculated using the following equation: Pl(cu) = i2l(RmS) RWinDing where IL(RMS) is the RMS inductor current that can be calculated as follows: Il(RmS) = iOut(max) 1+ 3 7
Fs = switching frequency KR = ratio of the AC inductor ripple current to the maximum output current The peak to peak inductor ripple current is: VOut (Vin(max) - VOut) Ipp= Vin(max)*Fs*L Once the required inductor value is selected, the proper selection of core material is based on peak inductor current and efficiency requirements. The core must be large enough not to saturate at the peak inductor current
(
Ipp IOut(max)
)
2
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SP7652 Wide Input Voltage Range 6A, 600kHz, Buck Regulator
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Output Capacitor Selection
APPLICATIONS INFORMATION VOut =
The required ESR (Equivalent Series Resistance) and capacitance drive the selection of the type and quantity of the output capacitors. The ESR must be small enough that both the resistive voltage deviation due to a step change in the load current and the output ripple voltage do not exceed the tolerance limits expected on the output voltage. During an output load transient, the output capacitor must supply all the additional current demanded by the load until the SP7652 adjusts the inductor current to the new value. In order to maintain VOut, the capacitance must be large enough so that the output voltage is held up while the inductor current ramps up or down to the value corresponding to the new load current. Additionally, the ESR in the output capacitor causes a step in the output voltage equal to the current. Because of the fast transient response and inherent 100% to 0% duty cycle capability provided by the SP7652 when exposed to output load transient, the output capacitor is typically chosen for ESR, not for capacitance value. The ESR of the output capacitor, combined with the inductor ripple current, is typically the main contributor to output voltage ripple. The maximum allowable ESR required to maintain a specified output voltage ripple can be calculated by: RESR VOUT IPK-PK where: Vout = Peak-to-Peak Output Voltage Ripple Ipk-pk = Peak-to-Peak Inductor Ripple Current The total output ripple is a combination of the ESR and the output capacitance value and can be calculated as follows:
(
IPP (1 - D) COutFS
)
2
+ (IppRESR)2
FS = Switching Frequency D = Duty Cycle COut = Output Capacitance Value
Input Capacitor Selection
The input capacitor should be selected for ripple current rating, capacitance and voltage rating. The input capacitor must meet the ripple current requirement imposed by the switching current. In continuous conduction mode, the source current of the high-side MOSFET is approximately a square wave of duty cycle VOut/Vin. Most of this current is supplied by the input bypass capacitors. The RMS value of input capacitor current is determined at the maximum output current and under the assumption that the peak to peak inductor ripple current is low; it is given by: Icin(RmS)= iOut(max) D(1-D) The worse case occurs when the duty cycle D is 50% and gives an RMS current value equal to IOut/2. Select input capacitors with adequate ripple current rating to ensure reliable operation. The power dissipated in the input capacitor is: Pcin=i2cin(RmS) RESR(cin) This can become a significant part of power losses in a converter and hurt the overall energy transfer efficiency. The input voltage ripple primarily depends on the input capacitor ESR and capacitance. Ignoring the inductor ripple current, the input voltage ripple can be determined by:
(c) Copyright 2006 Sipex Corporation
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SP7652 Wide Input Voltage Range 6A, 600kHz, Buck Regulator
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APPLICATIONS INFORMATION High crossover frequency is desirable for IOut(max) VOut (Vin-VOut) fast transient response, but often jeopardizes Vin=iOut(max) RESR(cin)+ FScinVin2 the system stability. Crossover frequency The capacitor type suitable for the output cashould be higher than the ESR zero but pacitors can also be used for the input capaciless than /5 of the switching frequency. tors. However, exercise additional caution The ESR zero is contributed by the ESR when tantalum capacitors are used. Tantalum associated with the output capacitors and capacitors are known for catastrophic failure can be determined by: when exposed to surge current, and input capacitors are prone to such surge current z(ESR) = when power supplies are connected "live" 2 COUT RESR to low impedance power sources.
.
Loop Compensation Design
The open loop gain of the whole system can be divided into the gain of the error amplifier, PWM modulator, buck converter output stage, and feedback resistor divider. In order to cross over at the selected frequency FCO, the gain of the error amplifier compensates for the attenuation caused by the rest of the loop at this frequency. The goal of loop compensation is to manipulate loop frequency response such that its gain crosses over 0db at a slope of -20db/ dec. The first step of compensation design is to pick the loop crossover frequency.
Type iii v oltage Loop Compensation G AMP (s) Gain Block v ReF (volts)
The next step is to calculate the complex conjugate poles contributed by the LC output filter, P(LC) = 2 L COUT
When the output capacitors are of a Ceramic Type, the SP7652 Evaluation Board requires a Type III compensation circuit to give a phase boost of 180 in order to counteract the effects of an underdamped resonance of the output filter at the double pole frequency.
PWM stage G PWM Gain Block v in v RAMP_PP [s^2LC (sR
oUT
output stage G oUT (s) Gain Block
esR
+ _
(sRz2Cz2+1)(sR1Cz3+1) sR1Cz2(sRz3Cz3+1)(sRz2Cp1+1)
C oUT + 1)
+s(R esR +R DC) C oUT +1]
v oUT (volts)
notes: R esR = output Capacitor equivalent series Resistance. R DC = output inductor DC Resistance. v RAMP_PP = sP6132 internal RA MP Amplitude Peak to Peak v oltage. Condition: Cz2 >> Cp1 & R1 >> Rz3 output Load Resistance >> R esR & R
DC
voltage Feedback G FBK Gain Block R2 v FBK (volts) (R 1 + R 2 ) or v ReF v oUT
SP7652 Voltage Mode Control Loop with Loop
Definitions:
RESR = Output Capacitor Equivalent Series Resistance RDC = Output Inductor DC Resistance RRAMP_PP = SP7652 internal RAMP Amplitude Peak to Peak Voltage
Conditions:
CZ2 >> Cp and R >> RZ3
Output Load Resistance >> RESR and RDC
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APPLICATIONS INFORMATION
Gain (dB) error Amplifier Gain Bandwidth Product Condition: C22 >> CP1, R1 >> RZ3
20 Log (RZ2/R1)
/2(Rz2)(CP1)
/2(Rz3)(Cz3)
/2(R22)(Cz2)
/2(R1)(Cz3)
/2(R1)(Cz2)
Frequency (Hz)
Bode Plot of Type III Error Amplifier Compensation.
CP1
RZ3 V OUT R1 68.1k, 1%
CZ3
CZ2
RZ2
R
5 VFB SET
+ + - 0.8V
6 COMP CF1
R
SET
=54.48/ (V OUT -0.8) (k)
Type III Error Amplifier Compensation Circuit
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SP7652 Wide Input Voltage Range 6A, 600kHz, Buck Regulator
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SP765X Thermal Resistance
APPLICATIONS INFORMATION
SP765X Thermal Resistance 4 Layer Board: Top Layer 3ounces Copper GND Layer 1ounce Copper Power Layer ounce Copper Bottom Layer 3ounces Copper Minimum Footprint: 44C/W Top Layer: 0. square inch No Vias to other 3 Layers Medium Footprint: 36C/W Top Layer: 0.7 square inch Vias to other 3 Layers Maximum Footprint: 36C/W Top Layer: .0 square inch Vias to other 3 Layers
The SP765X family has been tested with a variety of footprint layouts along with different copper area and thermal resistance has been measured. The layouts were done on 4 layer FR4 PCB with the top and bottom layers using 3oz copper and the power and ground layers using oz copper. For the Minimum footprint, only about 0. square inch (of 3 ounces of) Copper was used on the top or footprint layer, and this layer had no vias to connect to the 3 other layers. For the Medium footprint, about 0.7 square inches (of 3 ounces of) Copper was used on the top layer, but vias were used to connect to the other 3 layers. For the Maximum footprint, about .0 square inch (of 3 ounces of) Copper was used on the top layer and many vias were used to connect to the 3 other layers. The results show that only about 0.7 square inches (of 3 ounces of) Copper on the top layer and vias connecting to the 3 other layers are needed to get the best thermal resistance of 36C/W. Adding area on the top beyond the 0.7 square inches did not reduce thermal resistance. Using a minimum of 0. square inches of (3 ounces of) Copper on the top layer with no vias connecting to the 3 other layers produced a thermal resistance of 44C/W. This thermal impedance is only 22% higher than the medium and large footprint layouts, indicating that space constrained designs can still benefit thermally from the Powerblox family of ICs. This indicates that a minimum footprint of 0. square inch, if used on a 4 layer board, can produce 44C/W thermal resistance. This approach is still very worthwhile if used in a space constrained design. The following page shows the footprint layouts from an ORCAD file. The thermal data was taken for still air, not with forced air. If forced air is used, some improvement in thermal resistance would be seen.
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SP7652 Wide Input Voltage Range 6A, 600kHz, Buck Regulator
(c) Copyright 2006 Sipex Corporation
APPLICATIONS INFORMATION
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TYPICAL PERFORMANCE CHARACTERISTICS
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TYPICAL PERFORMANCE CHARACTERISTICS
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PACkAGE: 26 PIN DFN
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ORDERING INFORMATION
Part Number Temperature Package
SP7652ER ............................................... -40C to +85C .................................. 26 Pin 7 X 4 DFN SP7652ER-L ............................................ -40C to +85C ...............(Lead Free) 26 Pin 7 X 4 DFN SP7652ER/TR ......................................... -40C to +85C .................................. 26 Pin 7 X 4 DFN SP7652ER-L/TR ...................................... -40C to +85C ...............(Lead Free) 26 Pin 7 X 4 DFN
Bulk Pack minimum quantity is 500. /TR = Tape and Reel. Pack quantity is 3,000 DFN.
Sipex Corporation Headquarters and Sales Office 233 South Hillview Drive Milpitas, CA 95035 TEL: (408) 934-7500 FAX: (408) 935-7600 Sipex Corporation reserves the right to make changes to any products described herein. Sipex does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. Rev F: /0/06 SP7652 Wide Input Voltage Range 6A, 600kHz, Buck Regulator (c) Copyright 2006 Sipex Corporation
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